Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced nodes. In this paper, we extracted the parasitic and intrinsic capacitances of silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt accurately compare its and, consequently, circuit-level performances comparable Analytical models transistor were derived techniques such as equivalent Schwarz-Christoffel transformation standard cylindrical capacitors show close agreement with simulations. The maximum capacitance is $2\times $ larger than for 15 nm High Performance (HP) due TIGFET’s two additional gated contacts, but countered by ability multiple modes operation which reduces effective switching per device. A sees, on average, only 30% increase total compared HP Additionally, increased functionality can be used modify architecture TIGFET-based design mitigate performance impact device-level capacitance. This combination (1) operation, (2) lead enhanced system performance. particular, node has 18% lower energy-delay product fan-out 4 higher when 1-bit full-adder logic circuit HP.